Develops and markets SOCarchitect, a physical planning tool providing architects and chip designers with a visual environment for architecting complex IC and system-on-chip (SOC) designs. Includes product specifications, company news and industry links.
http://www.icinergy.com/
The company provides EDA solutions that enable electronic system designers to verify their algorithms in real hardware environments at an early design stage using C/C++/SystemC.
http://www.dynalith.com/
To purchase the book "The Art of Verification with Vera" online.
http://www.verificationcentral.com
Develops InstaCell, a semiconductor-based prognostic cell monitor that predicts end-of-life failure of electronic circuits and improves system reliability.
http://www.ridgetop-group.com/
The Spyglass suite of tools uses predictive analysis technique that performs structural analysis on Verilog and VHDL RTL to detect design problems in SoCs and ASICs.
http://www.atrenta.com/
This company provides solutions for hardware verification using Verilog.
http://www.fintronic.com/
ESP is an event driven Verilog symbolic simulator. ESP increases functional coverage and reduces verification runtime. ESP is ideal for memory and block level verification.
http://www.innologic-systems.com
A merging of design software companies, which creates a complete PC based design environment. This includes everything from ASIC design to PCB design.
http://www.innoveda.com