a version of Source Navigator that works with Verilog. Provides class and hierarchy views of Verilog designs.
General Verilog resource that includes a FAQ, tutorials, and commercial information.
Verilog FAQ: Includes answers to frequently asked questions and lots of links to other useful sites.
VHDL, Verilog and FPGA training courses held in the US, Europe and the UK.
Information on vhdl verilog and synthesis resources around the web. Includes tutorials, models and code generators.
Confluence language development, designer resources, and other free frontend EDA tools.
Andy Rushton, ECS Deartment, Southampton University. Web site for the book "VHDL for Logic Synthesis" and for a mini-FAQ for VHDL users.
A Verilog-HDL OnLine training course. This is an interactive, self-directed introduction to the Verilog language complete with examples and exercises. It covers the full language, including UDPs and PLI.