Offering a full suite of VHDL and Verilog design tools, from design-entry, simulation and synthesis to verification and training.
http://www.saros.co.uk/
A simple introduction to digital design using Verilog; thus, many features of verilog itself are left uncovered.
http://oldeee.see.ed.ac.uk/~gerard/Teach/Verilog/
Written in VHDL.
http://www2.latech.edu/~acm/helloworld/VHDL.html
A synthesys tool, which will optimize your ASIC/FPGA/CPLD design. Evaluation license is available.
http://www.exemplar.com/leonardospectrum/
Visual Digital Timing Analysis VHDL/Verilog from Chronology Corp.
http://www.chronology.com/
Overview of the ABEL Hardware Description Language.
http://www.ee.upenn.edu/rca/software/abel/abel.primer.html
from Green Mountain Computing Systems.
http://www.gmvhdl.com/
VHDL compiler and simulator from the University of Pittsburg.
http://www.servtech.com/~tcmayo/things/computers/programming/