VHDL and Verilog

Electronics Infoline Web

Synopsys Logic Synthesis

VHDL Compiler

http://www.synopsys.com/products/logic/logic.html

JHDL is a method of describing (programmatically, in JAVA) the components and connections in a digital logic circuit.

http://www.jhdl.org/

A VHDL simulator and implements nearly all VHDL87 and some features of VHDL93. GHDL is written in Ada95 and it is a GCC front-end. [Open source, GPL]

http://ghdl.free.fr/

Emacs/XEmacs mode for editing VHDL code.

http://opensource.ethz.ch/emacs/vhdl-mode.html

VHDL and ASIC / FPGA training courses as well as design services.

http://www.drvhdl.com/

Your one stop source for Verilog Programming Language Interface (PLI) resources

http://www.angelfire.com/ca/verilog/

a tool which converts state diagrams into synthesizable VHDL

http://www.servtech.com/~tcmayo/things/computers/programming/brusey20.html

Definitions, resources, and links related to hardware description languages.

http://en.wikipedia.org/wiki/Hardware_description_language