Offers a design and verification environment for C/C++ with synthesis to VHDL and Verilog code.
http://www.cleveldesign.com/
Altera's HDL.
http://www.altera.com/support/examples/ahdl/ahdl.html
A synthesizable 8051 model
http://www.cs.ucr.edu/~dalton/i8051/
The ForSyDe (Formal System Design) methodology has been developed with the objective to move system design to a higher level of abstraction and to bridge the abstraction gap by transformational design refinement.
http://www.ele.kth.se/ForSyDe/
Links to many programming languages, including several HDLs.
http://tos.maintree.com/titivillus/softwaredev.asp
Web based verilog generation tools for the common tasks such as crc and lfsr. Also contains links of interest to asic designers.
http://www.employees.org/~surendra/asic/
An intellectual property provider that develops and supports synthesizable cores and simulation models for electronic design using VHDL.
http://www.cast-inc.com/
This is a VDHL implementation of a pipelined DES encryption system.
http://www.yordas.demon.co.uk/crypto/