This is the home page for a Freeware Verilog,VHDL and Analog Mixed Signal project (a.k.a. the V-2000 project, still in its infancy).
http://www.v-ms.com/
Introduction to VHDL verification techniques. It assumes some familiarity with VHDL.
http://www.stefanvhdl.com/
RHDL (Ruby Hardware Description Language) is an HDL based on the Ruby programming language.
http://www.aracnet.com/~ptkwt/ruby_stuff/RHDL/
Bluespec adds extensions on to System Verilog to raise the abstraction level for complex control logic.
http://www.bluespec.com/
Designer's guides and models for VHDL and Verilog. SystemC home. Also Perl and Tcl/Tk for hardware designers resources.
http://www.doulos.com/knowhow/
The project goals are to develop a VHDL simulator that:``Has a graphical waveform viewer; has a source level debugger; is VHDL-93 compliant; is of commercial quality.
http://www.freehdl.seul.org/
Verilog models (in .exe format) of 16 MB DRAMs
http://www.moselvitelic.com/sec2/v53_16M.html
MyHDL is a Python package for using Python as a hardware description and verification language.
http://www.jandecaluwe.com/Tools/MyHDL/Overview.html