The iValidate toolset comprises ready-to-use functional verification tools and simulation models.
http://www.imodl.com/
Based on the IEEE 1364-1995 standard by Stuart Sutherland of Sutherland HDL, Inc.
http://www.sutherland-hdl.com/on-line_ref_guide/vlog_ref_top.html
On-Line Documentation.
http://www.ascinc.com/
A free perl script that converts verilog to html with most things linked. Also creates hierarchies and indexes for your design.
http://www.burbleland.com/v2html/v2html.html
HDL Graphical Editor-Text Editor from Translogic.
http://www.translogiccorp.com/
UCLA/ABKgroup Physical Design Tools for VHDL.
http://nexus6.cs.ucla.edu/software/PDtools/
Introduction to VITAL '95
http://vhdl.org/vi/vital/wwwpages/steves/
Provides tools for aiding Verilog development. Including The Temporal Rover for automatic verification of protocols and Verilog Java PLI.
http://www.time-rover.com/