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Delay line implements clock doubler








 
Delay line implements clock doubler
using a 5-nsec delay unit, a 50- MHz, 50% duty-cycle square-wave input produces a 100-MHz, 50% duty-cycle output clock

Authored by Y Li at EDN : Voice of theElectronics Engineer, Added: Mar 8, 2004



http://www.edn.com/archives/1996/071896/15di7.htm

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