The circuit is an implementation of a flicker noise generator described in NBS technical note 604, Efficient Numerical and Analog Modeling of Flicker Noise Processes by J.A.
Barnes and Stephen Jarvis, Jr. With the values shown the circuit will give a 1/f noise slope from below one hertz to over four kilohertz. The circuit employs a TLC2272 op-amp although other high impedance, low noise op-amps will work. The amplifier must have low noise current since a farily high value resistor is used to generate the 50 nV white noise; choose an op-amp with noise voltage less than 15 nV/root-Hz and noise current less than 0.1 pA/root-Hz, both easily obtained with several modern op-amps. The capacitor values vary slightly from the calculated values in the referenced paper to simplify construction and the circuit includes bias to allow the use of polarized electrolytic capacitors. The electrolytic capacitors should be selected carefully since many aluminum electrolytics have poor tolerances.
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