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Computer Z80 Project

Computer Z80 Project

Zilog Z80 processor, running at a blistering 20Mhz, Huge 16Kb Flash-based ROM, Enormous 48Kb block of SRAM, Serial interface via 16C550 UART or MAX232, ATA (IDE) hard disk or CD-ROM interface, Built-in bogon-resistant hardware, Unobtainium alloy chassis.
Basic Hardware

The backboard of the panel was cut from a 4mm piece of MDF. I used a draft print-out of the panel taped onto this to mark the centres of all the holes with a punch before drilling these out. I then printed off a good copy of the panel graphics, laminated it, and cut out the necessary holes with a scalpel. The switches are all of the panel-mount type and therfore came with fasteners with which to attach them to the board. The data and address bus LEDs were however mounted using small bits of stripboard, along with their resistors. The black bezels visible on the photo are LED holders, but most of these are just pushed into place; The LEDs are not clipped into the back. My excuse for the less-than-straight lines is that the holes where made with a hand-held drill and were therefore subject to occasional wandering!

Electronics

Designing the circuitry required to interface the front panel to the system turned out to be more challenging that initially expected. The first design involved using a few tristate latches to store the values of what would essentially be the address and data registers, plus a bit of glue logic to generate the appropriate control bus signals depending on the positions of the switches. Such a configuration would however have required much more work from the user to get anything done as the address bus would need to be toggled in for every single location. This would make sequential reading and writing very laborious.

The vital improvement was the automatic incrementation of the address on every read or write operation, as decribed above. This means a starting address can be toggled in and all subsequent reads and writes cause the address bus to skip to the next location automatically, ready for the next byte. This improvement did however add to the complexity as four 4-bit counters would be required to keep track of the value, as opposed to two 8-bit latches. Even worse, the counters can’t be connected directly to the address bus, so a tristate buffer was required.

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