PLLs are useful in a variety of applications, most notably cable and TV tuners. In these systems, the PLL synchronizes an output signal (typically from a VCO) with a reference or input signal, in frequency as well as in phase. The VCO in these PLLs requires a biasing circuit.
Depending on the VCO, this biasing circuit must provide an output voltage of 24 to 32V from an input voltage of typically 5, 9, or 12V. A low-cost VCO-biasing circuit converts a 5V input to a 27V bias-level output.
Timing capacitor CT sets the switching frequency. A value of 680 pF sets the switching frequency to 100 kHz. Capacitor CF (typically 10 to 25 pF), together with feedback resistors RF1 and RF2, provides compensation. You can find more details on the choice of these components in the LM3578A data sheet. With a slight modification, the same circuit works with a 9 or 12V input. The circuit simply requires a higher voltage input capacitor and a higher value inductor. Because the current requirements are so low, you can use inexpensive inductors and capacitors. Capacitor CIN2 suppresses the switching noise; you can use an inexpensive filter to further suppress the noise. The noise is a function of the ESR of the input and output capacitors. The circuit in Figure 1 is easy to implement using a 2-to-1-scale pc-board layout. (DI #2110).
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