. The design to be presented here is a simple PLC based on a classic FSM circuit with 8 TTL outputs and 7 inputs. The circuit should in fact be instantly recognizable to many. This design, while being quite versatile, has traditionally had one limitation, and that is the difficulty in generating the binary code used for the operation of the PLC. The benefit of this new design lies with the associated compiler program that converts a simple text based “IF/THEN” source code into binary code used for the EPROM. This allows anyone familiar with simple programming techniques to program a moderately complex PLC without learning a microcontroller programming language. The design does however require that you have access to an EPROM programmer that can program 27256 EPROM’s.
As can be seen from the circuit diagram, the design consists of little more than an EPROM, latch, buffer, and oscillator. The design is based on the classic FSM circuit which consists of memory and a latch which feeds the outputs back to the memory address inputs.
The key to the operation of the circuit is the 8 EPROM outputs that are fed back to the first 8 address lines (A0-A7) on the EPROM via latch IC2. Disregarding the other EPROM address inputs (A8-A14) for a minute, you can see how the EPROM can go from one state to the next. A “state” is simply one possible output condition, and in this instance with 8 data outputs we can have 256 possible states.
Let’s assume that the latch outputs are all LOW, which we’ll call the current state. This presents all LOW’s to the address inputs which represents address 0. Now, the data byte programmed into the EPROM at address 0 will be present on the EPROM data outputs, and will be latched into IC2 the next time IC2 is clocked. Thus the FSM has just changed state. The process continues again, for the next state. You will notice that if the data byte at address 0 was actually 0, then the FSM would stay in that state indefinitely
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