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Implementing Sleep Control for low­-power Cortex-­M1 systems

Implementing Sleep Control for low­-power Cortex-­M1 systems

The ARM Cortex-M1 processor implements the ARMv6-M architecture, which includes a Wait For Interrupt (WFI) instruction. The ARMv6-M architecture defines the WFI instruction as a NOP-compatible hint, which means that an implementation can execute it as a No Operation (NOP) instruction.

When a processor that supports WFI executes the WFI instruction, it suspends execution and enters a low-power state. When a processor that does not support WFI executes the WFI instruction, it has no effect because it executes as NOP. This ensures code compatibility between different processors.

The ARM Cortex-M1 processor always executes the WFI instruction as a NOP. However, if your application requires power management support it is possible to implement an external sleep controller that puts the processor into a similar low-power state. This Application Note describes how you can implement an external sleep controller for the ARM Cortex-M1 processor.

Before reading this Application Note, you should make sure that you are familiar with:

  • the ARM Cortex-M1 processor
  • the AMBA3 AHB-Lite protocol.

 

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