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PLL & PLLVCO Serial Programming Interface (SPI) Mode Selection Design Considerations

PLL & PLLVCO Serial Programming Interface (SPI) Mode Selection Design Considerations

This application note discusses best practices for use of the Serial Port Interface (SPI) Mode selection feature of Hittite’s PLL and PLLVCO product lines. In this note, we will refer to them all, simply as the PLL/VCOs.

The PLL/VCO devices covered in this document support two different serial interface modes or protocols: Open Mode and HMC Mode.

The serial interface mode selection occurs after power-up and Power-On-Reset (POR) in the PLL/VCO. The PLL/VCO is reset and ready for mode selection after an internal Power-On-Reset occurs, automatically about 450 µsec after the PLL/VCO digital supply rises past half of its nominal value. The mode selection is then determined by the first occurrence of a rising edge on either the SCK (Open Mode) or SEN (HMC Mode) after the POR event.

Once the mode is selected on the initial bus transaction, the mode cannot be changed without powering down the power supply. Activity on the SPI lines prior to POR is ignored assuming both MPU and the PLL/VCO are powered up at the same time.

It should be noted that circuits with VCO subsystems, such as the RF PLLVCOs have a second POR circuit in the VCO subsystem on the VCC2 supply. The POR in the VCO subsystem does not affect mode selection but it does affect proper operation of the VCO and has certain conditions for minimum rise time, and maximum voltage on start up. It is typically recommended to be less than 1 msec rise time and less than 150mV on startup.

 




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