Zero Latency Multiplexing I/O for ASIC Emulation (PDF!) application note from Xilinx:
This application note provides a method for FPGA emulation platforms to communicate multiple signals over one I/O or I/O differential pair to another FPGA. This multiplexing method serializes data up to 800 Mb/s without introducing any additional cycles of latency to the user who is running at a slower rate.
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