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App note: Understanding latch-up in advanced CMOS logic

App note: Understanding latch-up in advanced CMOS logic

Another old app note from Fairchild Semiconductor about CMOS latch-up. Link here (PDF!)

Latch-up is a failure mechanism of CMOS integrated circuits characterized by excessive current drain coupled with functional failure, parametric failure and/or device destruction. It may be a temporary condition that terminates upon removal of the exciting stimulus, a catastrophic condition that requires the shutdown of the system to clear or a fatal condition that requires replacement of damaged parts. Regardless of the severity of the condition, latch-up is an undesirable but controllable phenomenon. In many cases, latch-up is avoidable.

Latch-up has long been a bane to CMOS IC applications; its occurrence and theory have been the subjects of numerous studies and articles. The applications engineer and systems designer, however, are not so much concerned with the theory and modeling of latch-up as they are with the consequences of latch-up and what has been done by the device designer and process engineer to render ICs resistant to latch-up. Of equal interest are those precautions, if any, which must be observed to limit the liability of designs to latch-up.

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