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App note: Isolation design flow for Xilinx 7 series FPGAs or Zynq-7000 AP SoCs (ISE Tools)

App note: Isolation design flow for Xilinx 7 series FPGAs or Zynq-7000 AP SoCs (ISE Tools)

Xilinx application note, Isolation design flow for Xilinx 7 series FPGAs or Zynq-7000 AP SoCs (ISE Tools) (PDF!)

This application note is written for FPGA designers wishing to implement security or safety critical designs, that is, information assurance (single chip cryptography), avionics, automotive, and industrial applications, using the Xilinx Isolation Design Flow (IDF). This document explains how to:

• Implement isolated functions in a single Xilinx 7 series FPGA or Zynq®-7000 All Programmable SoC (AP SoC)(1) in commercial-grade or defense-grade using IDF.
° For example, implementation might include red/black logic, redundant Type-I encryption modules, or logic processing multiple levels of security.
• Verify the isolation using the Xilinx Isolation Verification Tool (IVT).

With this application note, designers can develop a fail-safe single chip solution using the Xilinx IDF that meets fail-safe and physical security requirements for high-grade, high-assurance applications.

 

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