This application note is written for FPGA designers implementing the single-chip crypto (SCC) technology developed by Xilinx. This document explains how to:
With this application note, designers can develop a single-chip cryptographic solution that meets fail-safe and physical security requirements for high-grade, high-assurance applications.
The Security Monitor IP developed by Xilinx provides additional security services for Virtex-5 and Virtex-5Q FPGAs. Contact your local Xilinx representative for more information.
Type 1 Virtex-5 FPGA Crypto applications require defense-grade (XQ) devices for mask control. The design example used in this application note was created using a non defense- grade Virtex-5 XC5VLX85-FF676-2 device.
Read more Here