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Developing Secure Designs Using the Virtex-5 Family

Developing Secure Designs Using the Virtex-5 Family

This application note is written for FPGA designers implementing the single-chip crypto (SCC) technology developed by Xilinx. This document explains how to:

  • Implement isolated functions (for example, red/black logic, redundant Type-I encryptors or logic processing multiple levels of security) in a single Virtex®-5 or Virtex-5Q FPGA.
  • Verify the isolation using the Xilinx® Isolation Verification Tool (IVT).

With this application note, designers can develop a single-chip cryptographic solution that meets fail-safe and physical security requirements for high-grade, high-assurance applications.

The Security Monitor IP developed by Xilinx provides additional security services for Virtex-5 and Virtex-5Q FPGAs. Contact your local Xilinx representative for more information.

Type 1 Virtex-5 FPGA Crypto applications require defense-grade (XQ) devices for mask control. The design example used in this application note was created using a non defense- grade Virtex-5 XC5VLX85-FF676-2 device.

 




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