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Basic Frequency Meter with FPGA , Verilog HDL , WireFrame FPGA

Basic Frequency Meter with FPGA , Verilog HDL , WireFrame FPGA
In the series of learning FPGA project , Gaurav presents here a simple little project to measure frequency with counter and few 7 segment display.

Theory Of operation

there is nothing much to it actually , you need a counter (count)  which increments with the rising edge of input signal (sigin)  and you have to have a control (gate) through gate when counter counts when it does not. so if you keep gate open for 1sec flat , so after 1sec the value you have with the counter (count ) is your frequency.
lets look at this timing diagram , it has a signal input sigin, gate pulse gate, counter value count , frequency display freq,
the gate goes high (active ) for a fixed amount of time ,1 Second ,when gate is high(active) counter start increment on every rising edge of the sigin  and keep on increment till gate is high , as soon as gate goes low , counter stop at the value how many rising edge was there in the sigin during the gate was high(active) .  as gate time is 1 Second so what ever value is there in the count is your frequency ,
Now we need to update this value to frequency display . as soon as gate time expires it put the value of count to frequency display register.
for next sample gate pulse again go high and clear the count register also.
Verilog Model 

 first of all you need a counter , which increment on input and give a ouput ,

 

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