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Assess Power-Supply Noise Rejection in Low-Jitter PLL Clock Generators

Assess Power-Supply Noise Rejection in Low-Jitter PLL Clock Generators

This article discusses the effects of power-supply noise interference on PLL-based clock generators, and describes several measurement techniques for evaluating the resulting deterministic jitter (DJ). Derived relationships show how frequency-domain spur measurements can be used to evaluate timing-jitter behavior. Laboratory bench-test results are used to compare the measurement techniques, and demonstrate how to reliably assess the power-supply noise rejection (PSNR) performance of a reference clock generator.

Clock generators that employ PLLs are widely used in network equipment for generating high-precision and low-jitter reference clocks or for maintaining a synchronized network operation. Most clock oscillators give their jitter or phase-noise specification using an ideal, clean power supply. In a practical system environment, however, the power supply can suffer from interference due to on-board switching supplies or noisy digital ASICs. To achieve the best performance in a system design, it is important to understand the effects of such interference.

First we will examine the basic power-supply noise rejection (PSNR) characteristics of a PLL-based clock generator. We will then explain how to extract timing-jitter information from measurements taken in the frequency domain. These techniques are then applied and several different measurement methodologies are compared using lab bench testing. Finally, we will summarize the merits of the preferred approach.