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All Digital VCXO Replacement Using a Gigabit Transceiver Fractional PLL

All Digital VCXO Replacement Using a Gigabit Transceiver Fractional PLL

This application note delivers a system that is designed to replace external voltage-controlled crystal oscillator (VCXO) circuits by utilizing functionality within the gigabit transceiver and associated PLLs.

A common design requirement is to frequency or phase lock a transceiver output to an input source (known as loop, recovered, or slave timing). Traditionally, an external clock cleaning device or VCXO and PLL components are used to provide a high-quality clock reference for the transceiver, since FPGA logic-based clocks are generally too noisy. While effective, external clock components carry a power and cost penalty that is additive as each individual clock channel is generated. When using many channels or in low-cost systems, the cost can be significant. Additionally, adding many external clock sources provides more opportunity for crosstalk and interference at the board level.

The system described in this application note provides a method to effectively replace these external clock components with the Xilinx transceiver fractional PLL (fPLL) when used in conjunction with a high-performance FPGA based digital PLL (DPLL). Each Quad PLL (QPLL) has the capability to be fractionally frequency controlled using a dedicated interface. The QPLL has an interface that controls a sigma delta modulator (SDM) to enable the fractional feedback capability in the QPLL. The main QPLL feedback is controlled fractionally based on the SDM control word allowing fine frequency control by modulating the ratio of the feedback between N and N+1. The control input can be set statically or controlled dynamically from an FPGA logic-based DPLL system.

The reference design circuit provides a fully integrated DPLL and transceiver fPLL system which can be instantiated for each QPLL used. The QPLL nominal operating rate is set using an external crystal oscillator (XO), and using the fPLL feature the output can be phase- or frequency-locked to an input reference signal. The DPLL enables generation of a synchronous QPLL output with run-time configurable parameters (e.g., gain, cutoff frequency, and clock divider values) to enable you to set up the operation specifically for the end application. This allows the flexibility of the reference input signal and DPLL cleaning bandwidth.

 

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