Greetings — a short, first post for 2016 !
In numerous RF synthesizer chips lies an inverter with input and output pins for making a reference crystal oscillator clock. I built some discrete chip inverter xtal oscillators with 74HC series logic gates to better examine them. You’ll quickly recognize the oft-used Pierce oscillator topology with 1 trimmer capacitor to tweak the fundamental frequency which might vary from factors like crystal aging and gate, crystal, crystal holder + board reactances.
I determined the 27 pF and trimmer cap values through experiments and measures.
Above — A crystal reference oscillator + buffer with inverters built from NAND gates. The crystal is a good 1 — built in 2013; AT- cut; parallel 20 pF load capacitance; fundamental 12.8 MHz; a measured QuL of 265K and zero spurs during my test sweeps. Further, this crystal ages < 5 ppm per annum for at least 2 decades.
If I contrast this with some cheap xtals I bought and tested from eBay — it’s night versus day. You might find such xtals in DDS and other low-cost synthesizers kits. They typically come in a HC-49S case, might suffer a QuL of 40-60K — and more alarmingly, those I measured often showed strong, close-in spurs to further trash the already compromised close-in phase noise of these low-cost synthesizers.
Quoting Dr. Ulrich Rohde ” [ALL] elements in a synthesizer contribute to noise. Two primary noise contributors are the reference and the VCO. Actually, the crystal oscillator or frequency standard is a high-Q version of the VCO” [ Reference 1 ].
Although this post isn’t about phase noise; in this era of poor quality, “cheapo” crystals, I think a low-noise reference is worth considering when synthesizing signals for specific applications that require low phase noise. Big thanks to Alexei Luk for sending me this 12.8 MHz gem.
I found a problem with my circuit as shown above: strong spikes on the positive and negative edges. My quest became finding ways to decrease these spikes and enhance the square waveform seen in my DSO
Above — My DSO screen capture of the NAND oscillator circuit show earlier. The edge peaks swings 9 Vpp. In 1 circuit they ran over 10.1 Vpp or double the rail to rail DC voltage. What’s this all about?
I emailed my circuit and measures to Professor Ken Kuhn who gave me some excellent suggestions which I’ll augment with experiments and apply in a circuit.
My favorite point from Ken: No matter how low the frequency you’re working at, design and construct your circuits like you’re operating them
So from Ken’s wisdom and a little of my thinking + experiments, here’s what I did:
 Because we’re operating a square wave oscillator, odd harmonics will run at high amplitude. The third harmonic at ~38.4 MHz was only 8-10 dB down from the fundamental in some of my frequency domain experiments. This means the power supply bypass cap should minimally bypass into lower VHF and go right on the DC power pin (14) with the shortest possible leads to keep its SRF as high as possible. The bypass cap should ideally offer high Q / low ESR at VHF.
 Apply compact construction to reduce stray C, L, — and to minimize distortion and start-up stabilization time. In particular, short ground lead lengths for the 27 pF and trimmer caps proved important to reduce my edge spikes The shorter the circuit wires, the better rings TRUE here.
 Although in synthesizer chips, we only get 1 inverter with 2 pins, for off-chip oscillators a buffer proves useful. A small series resistor between the oscillator output and the buffer input pins serves to dampen any resonance in the output circuit ( often in the 10s of MHz ) from excitation that causes the spikes you see as the inverter switches on and off. It’s affected by stray L and C around the IC.
 10X scope probe capacitance lowers the resonant frequency and boosts RF energy. To minimize this loading, you might tack solder a 100 Ω ( or so ) resistor onto the buffer output pin and attach the probe clip to this resistor. Experiment with the resistor values in  and  to find out what works best on your bench.
 The 27 pF cap and trimmer cap grounds should lie as close as possible to the IC ground pin.
 Don’t overdrive your crystal. I placed a 47 Ω resistor between the inverter output and the 27p capacitor/crystal lead and determined this R value experimentally by watching the trace and frequency counter in my DSO. Since the output resistance of the inverter driver is very low compared to the reactance of the capacitors and crystal ( the crystal , trimmer and 27 pF cap form a complex impedance ) the resistor isolates the output driver and also lowers the crystal drive level.
My crystal features high Q and the 74HC inverter drives it hard. Adding the resistor reduced the edge spikes slightly. Further I performed a test where I raised the DC supply voltage slightly and my signal appeared to distort and the frequency dropped slightly. The 47 Ω resistor removed this issue and stabilized my TTL inverter oscillator.
Here’s the final schematic:
Above — My final TTL Pierce gate oscillator design with a 100 Ω resistor to isolate the 10X DSO probe during measurement. On the 5 VDC line. A 22 µF + 100nF then 33 Ω resistor plus 1 nF capacitor on Pin 14 form a pi-filter for wide band, low-pass DC filtration from AF to lower VHF. VHF bypass on pin 14 helps quench edge spikes.
I learned another point from Ken about my earlier circuit with the NAND inputs shorted to make an inverter. It’s often better to bias 1 NAND input gate to high and then use the other input for the oscillator feedback connections (inverter mode operation). This halves the input capacitance seen by the feedback network and may result in less effect tuning effect on the IC in some applications.
I tried this —- and like when I connected the buffer inverter up, I had to adjust the trimmer cap to either re-establish high frequency oscillation, or set the desired oscillator frequency in my counter.
During my final experiments, I remembered that I purchased some 74HC14s in 2015 to build a simple HF sawtooth generator to externally quench a super regenerative receiver. The 74HC14 features 6 inverters with a Schmitt trigger input. Quickly, I built my oscillator around this chip. Further, I ordered 10 standard hex inverter 74HC04 chips for future projects. Logic ICs provide major fun!
Above — DSO output of the improved inverter crystal oscillator. I’m quite happy with the output voltage(s) and oscillation + frequency stability now.
I also read about and performed some temperature compensation experiments. Nothing worth mentioning however. For reference purposes, here’s a video of my uncompensated, board – on – bench 12.8 MHz clock into a HP, 10-digit, ovenized reference frequency counter.
Above — Video shot just after power up @ room temperature. The ( temperature ) frequency drift of my inverter crystal oscillator circuit appears good. This crystal will provide an excellent on-chip reference for an experimental PLL project I’m working on. The 12.8 MHz reference gets divided by 2048 in a PLL chip to achieve a tuning resolution of 6250 KHz.
Additional Bits and Pieces
Above — Testing a commercial 12.8 MHz oscillator by Vectron International. Great engineering coupled with with a fabulous crystal results in a typical phase noise of -140 dBc/Hertz @ a 10 KHz offset — perfect for a UHF reference clock.
Above — I’ve always got music playing in and around my lab. Since 2006 my favorite singer = Julia Savicheva. Twitter. All of December to January I listened to Julia for creative inspiration while working on my PLL experiments. No Auto-Tune on her voice; amazing band; hard working. She sounds equally good live or recorded — how refreshing!
 Synthesizer Design for Microwave Applications. Some notes published online by Dr. Ulrich L. Rohde. Year unknown.
 Professor Ken Kuhn. Email correspondence Jan 2016. My sincere thanks to Ken.
 An Analysis of Inverter Crystal Oscillators”, RF Design,Aug. 1989, Leonard L. Klein berg, pp. 28,29,3l,32.
 Negative Gain-Single Pole Oscillators, RF Design, Sep. 1990, Leonard L. Kleinberg, pp. 35, 36, & 38. Modern Communications