This application note describes a method for capturing asynchronous communication using SelectIO™ interface primitives. The method consists of oversampling the data with a clock of similar frequency (< ±10,000 ppm), taking multiple samples of the input data at different phases, and processing these to get a sample of the data at the most ideal point to give error-free data recovery.
The SelectIO interface performs 4x asynchronous oversampling using an IDDR primitive. Clocks are generated from an MMCM or PLL primitive and are routed through BUFG clock networks and can operate on single-ended or differential signaling using any chosen input within the device.
The example design provided with this application note is designed for an Artix®-7 XC7A200T-1FBG676C FPGA (-1 speed grade) running on an AC701 evaluation board. It is delivered as an IP repository block to be added to the Vivado® Design Suite IP catalog. The design uses about 20 LUTs per channel, operates at up to 200 Mb/s, and requires 400 MHz, 200 MHz, and 100 MHz clocks from an MMCM or PLL to provide data recovery at 200 Mb/s. The operating speed of the data recovery is determined by the applied clock speeds and can be readily modified provided the same overall clock ratios are maintained.
The design specifications are: