This document provides a reference design for customers on how to interface a DRAM with the SHARC DSP using a DRAM Controller. The controller is implemented as a state-machine on a Xilinx PLD. This design has been simulated, built in hardware, and tested to operate successfully. The design, however, has not been optimized for best performance.
Different applications require specific ways of DRAM interfacing. This design implements a DRAM controller to interface a 4 Meg DRAM by Micron with the SHARC.
DRAM is an ideal solution for mass data storage with high speed. However, DRAM requires page swapping if an access crosses a page boundary. In addition, DRAM requires refreshing so that data is retained properly. This means an external controller is needed to handle the interface between the Sharc processor and the DRAM.
The controller receives input signals from the Sharc on each memory access and asserts the right control signals to the DRAM to read or write. Eleven 2:1 mux’s are used to select between column address and row address depending on whether the controller is doing a page swap or a normal read/write. The refresh timer is responsible for telling the controller when to refresh the DRAM.
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