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MIPI D-PHY Solution with Passive Resistor Networks in Altera Low Cost FPGA

MIPI D-PHY Solution with Passive Resistor Networks in Altera Low Cost FPGA

The Mobile Industry Processor Interface (MIPI) is an industry consortium specifying high-speed serial interface solutions to interconnect between components inside a mobile device. The group specifies both protocols and physical layer standards for a variety of applications. The D-PHY is a popular MIPI physical layer standard for Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols. You can use the CSI-2 interface with D-PHY for the Camera (Imager) to Host interface, as a streaming video interface between devices, and in applications outside of mobile devices.

The D-PHY provides a synchronous connection between a master and slave. The minimum PHY configuration consists of a clock and one or more data signals. The D-PHY uses two wires per data lane and two wires for the clock lane. The lane can operate in a high-speed (HS) signaling mode for fast-data traffic and low-power (LP) signaling mode for control purpose.

The maximum data rate that can be supported in high-speed signaling is determined by the performance of the transmitter, receiver, and interconnect implementations. In practice, the typical implementation has a bit rate of approximately 500-800 Mbps per lane in high-speed mode for passive D-PHY. However, for some D-PHY applications, the bit rate can go up to 1.5 Gbps per lane. The maximum data rate in lowpower mode is 10 Mbps.

 

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