A 4-layer PCB stackup is strongly recommended for all Rf PCB layouts since it provides a complete ground plane and power plane and hence allows simpler routing of the signal lines. All unused areas of the signal layers are also to be covered with ground filling. The advantage of a 4-layer design over a 2-layer design is that a 4-layer design enables an evenly distributed Rf decoupling of a DC power plane sandwiched between two layers of predominantly ground plane. The ground planes on either side of the power plane should be stitched with vias. This arrangement significantly improves emi-emc performance. Also the stitching vias for ground planes are to be used at the edges of the board so that radiated emissions at the board edges are avoided. A continuous ground plane also ensures that the return path of the sensitive rf traces can take the shortest route and hence avoiding extended ground loops. The return current takes the path of least inductance. Hence there should be no discontinuities in the ground plane under the Rf trace, all the way from the driver to the receiver. A continuous ground plane also allows distributed microstrip traces to be employed and hence impedance of the traces (typically 50W) can be strictly controlled.
For those on a strict budget, a 2-layer design can also be successfully implemented with the bottom layer covered by a predominantly ground copper pour. Also the PCB thickness should be strictly controlled since in order to implement microstrip or stripline transmission lines, the PCB thickness should not exceed 0.8mm to 1.0 mm, since the width of the transmission line trace will otherwise become too large.
The ground plane, as far as possible, should be left free of signal routing.
Each Rf trace is to have a characteristic impedance of 50W. The right type of transmission line is to be chosen when calculating the trace width for a characteristic impedance of 50W. There are many companion apps available such as Saturn PCB toolkit and AppCAD which can be used for calculating the trace width and distance from the ground plane for the particular PCB stackup. The calculated trace width should be maintained throughout the length of the trace and for a CPWG, the distance of the trace from ground on either side, is also to be maintained throughout.
Do not run Rf traces in parallel. If such a case is unavoidable, make sure that the 3W rule is followed, which states that the center to center distance between the parallel traces should be equal to or greater than the 3 times the width of the trace in order to avoid crosstalk and noise coupling.
The number of vias on board is to be minimized as much as possible since it introduces parasitic inductance and capacitance to a trace. For a typical PCB thickness of 1.6mm, a single via can add 1.2nH of inductance and 0.5pF of capacitance depending on the dimensions of the via and the dielectric material. A via should never be shared between multiple pins of a component.
As far as possible make sure that the Rf traces are routed without bends. In the event of a bend being unavoidable, make it a curved bend instead of a sharp bend. This will help maintaining a uniform width.
Do not create stubs on Rf traces. Placing test points on Rf traces is also to be avoided since they form stubs. Stubs affect impedance matching and also act as antennas which could create radiated emission problems.
Wherever possible place ground guard traces around sensitive Rf circuits. Place stitching vias on these guard traces to stitch them to the ground plane. This arrangement isolates the sensitive circuit from other parts of the circuit.
Power supply decoupling is to be implemented to make sure that noise in the power supply is filtered and does not reach other sensitive devices. Ensure that ample decoupling capacitors are provided. Several capacitors in parallel may need to be provided, so that noise at different frequencies are filtered out. A capacitor which has a self-resonant frequency close to the frequency to be filtered would be most effective. Each decoupling capacitor should have its own via connection to ground. As is the standard practice, the decoupling capacitors are to be placed as close to the power port of the IC as possible. Additionally, a bulk capacitor can also be provided to meet the sudden inrush current needs of an IC. The power supply should be connected to the power pin of the IC in such a way that the power flows to the IC through the decoupling capacitor. Do not place any via between the capacitor and the IC power pin.
This tutorial is meant to be an introduction to the principles of Rf PCB design techniques. Proper design and layout of the PCB is critical to success of an RF circuit.