[By Stephen St. Michael, All About Circuits Website]
This article will introduce the Advanced Microcontroller Bus Architecture (AMBA), an open standard for SoC designs.
As semiconductor manufacturing has evolved, the ability to fit more logic gates on the same size die has steadily increased. Being able to include more and more components on the same chip led to the birth of the SoC, or system on a chip.
An SoC is typically defined as an integrated circuit that includes all the necessary elements that make up a computer. This includes the CPU, RAM, non-volatile storage, a UART, and any other peripheral that the system needs. With a plethora of different components all on the same chip, efficiently connecting and managing these subsystems quickly became a challenge.
The Advanced Microcontroller Bus Architecture (AMBA) is one attempt to solve this problem.
AMBA is an open-standard that outlines how to connect and manage the different components or blocks within an SoC. The AMBA specification was developed by ARM and has become the de facto standard for interfacing components in an SoC. While AMBA is currently on its 5th revision and has evolved significantly over time, legacy implementations are widely used and remain relevant. Keeping that in mind, this article will use Revision 2.0 as a starting point and build off of these ideas in a future article.
The AMBA specification was developed to solve some key problems in the design of an SoC. One of these is right-first-time development, meaning that if used correctly AMBA can ensure a coherent design from the beginning, reducing costly redesigns. Another key requirement of AMBA was technological independence or making designs reusable and agnostic to the specifics of system components. With modular system design, AMBA encourages the development of component libraries so that work done once need not be repeated. One final motivation of AMBA was to minimize how much silicon was needed for both on-chip and off-chip communications.
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In Revision 2.0 three distinct buses are described for facilitating on-chip communications. These are the Advanced High-Performance Bus (AHB), the Advanced System Bus (ASB), and the Advanced Peripheral Bus (APB). The AHB is the backbone of the system and is designed specifically for high performance, high-frequency components. This includes the connections of processors, on-chip memories, and memory interfaces among others.
The ASB is an alternative to the AHB where some high-performance features are not needed. The APB is a simplified interface designed for low bandwidth peripherals that do not require the high performance of the AHB or the ASB. These include components like a UART, low-frequency GPIO, and timers.
The AHB was a new addition to AMBA in revision 2.0. It was added to accommodate high-performance designs. Some of the new features added were split transactions, single-cycle bus master handover, single-clock-edge operation, and wider data bus configurations, i.e., 64/128 bits.
An AHB must contain a number of components outside of the masters and slaves. These components are an address and control multiplexer, a read multiplexer, a write multiplexer, a decoder, and an arbiter. Figure 2 shows three masters connected to four slaves on an AHB. The signals shown are the address signal (HADDR), the write data bus (HWDATA), and the read data bus (HRDATA). The address is used for slave selection, the write data bus is used to move data from master to slave, and the read data bus is for moving data between slave and master.
When a master needs to take control of the bus, it must first send a request to the arbiter.
The arbiter grants access based on a prioritization scheme that ensures masters with a higher priority are given access first. This prioritization scheme is not defined by AMBA and will differ between designs. A number of control signals are used to define the direction, width, and type of the data transfer. The AHB decoder receives the address signal from the master and decodes it into slave select signals. The slave responds to the master via an HRESP signal and the data transfer between master and slave begins.
In total, there are about 20 different AHB signals each with a unique purpose. Figure 3 shows the AHB signals alongside the ASB signals for reference.
The ASB is a simplified version of the AHB and offers high performance for 16- and 32-bit systems. Many of the same signals on an AHB are used for the ASB aside from certain control signals that allow for split transactions.
The operation of the ASB starts with a master requesting access to the bus from the arbiter. The arbiter grants the request and the transfer begins. The decoder decodes the address placed on the bus and selects a slave. The slave responds back to the master and the data transfer takes place.
The APB is a simplified interface for low-frequency system components. Revision 2 simplified the bus further by having all signal transitions synchronized to the clock’s rising edge.
The APB consists of a single bus master called the APB bridge, which acts as a slave on the AHB/ASB. Thus, the bridge is the interface between the high-performance bus and the low-frequency peripherals. The peripheral devices on the APB are the slaves. Figure 4 lists the APB signal names.
Figure 5 below shows an example AMBA system running with two AHB masters, an AHB slave, and two APB slaves. Notice the AHB arbiter, AHB decoder, and APB bridge, as well.
The APB bridge has an AHB slave interface, so it looks like another slave to the masters. This system has been simplified with some signals and minor elements (such as reset signals and multiplexers) removed. Output signals leave the right side of a block, and input signals enter the left side of a block. Input signals are also denoted by an arrowhead. Thicker lines represent larger data paths.
This system is performing a write to one of the APB slaves over the course of about seven clock cycles. The AHB is a pipelined bus and has dedicated read and write paths, so a read could happen partway through this write. For more accurate timing information consult the AMBA standard Revision 2.0.
Eventually, the AHB hit performance limits and by 2003 ARM had released a new generation of AMBA protocols. AMBA revision 3.0 introduced the AXI protocol. AXI stands for Advanced eXtensible Interface and offers even higher performance than the AHB, implemented through a point-to-point connection scheme. Instead of a system bus, the AXI interconnect allows transactions between masters and slaves using only a few well-defined interfaces.
In the next AMBA article, we will take a look at AXI3 and AXI4 and how these are used to interface SoC components.
In this article, we introduced the Advanced Microcontroller Bus Architecture or AMBA. AMBA is an open standard that outlines how components on an SoC can exchange data in a fast and efficient manner.
AMBA has become a de facto standard and is currently on its 5th revision. Starting with revision 2.0, we looked at the AHB, ASB, and APB and how they work from a high level. While much of these bus protocols have been supplanted by future revisions of AMBA, they remain relevant in legacy designs and as a foundation for future learning.
Whether you’re interested in SoC design professionally or as a hobby, AMBA is a crucial step along your journey.