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Ethernet Receiver

Ethernet Receiver

This project is an attempt to capture 10BASE-T (10Mbps) Ethernet packets using phase locked loop (PLL) clock recovery. This is not the best way to do it! FPGA is the way to go. This is really an exercise in PLL design. The challenge is to lock in less than 64 cycles (6.4 µs) which is the length of the 10BASE-T preamble.

This demands a fast response i.e. wide loop bandwidth. Also, at a comparison frequency of 10 MHz, gate propagation delays are significant and switching speed is critical. This is one PLL application, however, where phase noise is not a concern. Although it works, the design has some shortcomings as you will read. 

This is my interface to twisted pair. Even though I’m not transmitting packets, the hub (or whatever) at the other end will not talk to me unless I periodically send NLP link pulses. 

T2 is wired to invert the negative-going pulses produced by U8/C. I’m using an SI-10021 RJ45 connector with integral magnetics purchased from RS Components. The wiring shown is for connection to a hub via a “straight” cable. Either swap TD/RD, or use a “crossed” cable to a PC. 

Manchester encoding
Clock and data are combined by transmitting logic ‘0’ as 10 and logic ‘1’ as 01. There’s an edge in the middle of every bit. To allow receivers to synchronise, packets begin with a 64 bit preamble which is the sequence 101010… ending in 11: 

I’m using quadrature clocks. The rising edge of the In-Phase Clock (CLK I) falls in the centre of the data bit. Lock must be acquired during the preamble. The Quadrature Clock (CLK Q) can then be used to gate-out unwanted edges between data bits. 

My original plan was to use a voltage controlled crystal oscillator (VCXO). Unfortunately, as I discovered when I tried to design the loop filter, it’s impossible to achieve wide loop bandwidth using a VCXO. kVCO is too low. The answer was to use an LC oscillator. My circuit is based on one used by RACAL in the RA1772 communications receiver: 

L1, C6 and C7 form a capacitvely-tapped tuned circuit resonant at 20 MHz. The output at Q7 collector is almost square – ideal for logic. 
L2 is perhaps a little low. I tried a 10k resistor here but the loop response was too slow because it formed a low-pass filter with the input capacity of C7/C8. L2 must be small for the same reason. Unfortunately, it probably loads the tuned circuit reducing the Q somewhat. 

The measured transfer characteristic of the VCO is shown below: 

The slope is 320 KHz per volt after the divide-by-2. kVCO = 2 x 106 radians per volt-second. The linear region is not centred on 20MHz! 

The ’35Z varicap (1-8V / 535-22pF) is intended for AM Radio tuning! I tried a BB809 first but the response was too slow. Lock-in time dropped dramatically when I touched the ’35Z across it. kVCO was greatly increased because the ’35Z has a lot more pF per volt. 

The duty cycle of the 20 MHz signal is not 50/50. Because of this, and logic propagation delays, the clocks are not quite in quadrature. The oscillator could run at 40 MHz with an additional divide-by-2 preceding the quadrature generator. 

A charge pump using complementary PNP/NPN transistors follows a standard phase-frequency detector based on dual D-type flip-flops. U9/C gates-out the unwanted EDGE pulses at the phase comparator reference input: 

The charge pump has a current output of approximately ±3mA giving the overall phase detector a theoretical gain of kPD = 0.5 mA per radian. The exact value is hard to predict. Unfortunately, switching speed is a problem with this circuit. I added capacitor C15 to speed-up Q3 turn-on but it’s still slow at turning off. 

Another problem is imbalance between source and sink currents. The loop automatically corrects for this by running at a small constant phase error resulting in zero net charge output. Although small, the error was too much for the original lock detector. The voltage across C16 did not quite cross the lower logic threshold until I reduced R16 to 3k9. 

The duty cycle at the output of U8/b is a measure of the quality of lock. Ideally, it should be narrow spikes. The reset pulses from U9/D also look a bit wide. Gate propagation delays are significant at the 10 MHz comparison frequency. Substituting a 74F00 device improved matters slightly. 

Q6 pulls the VCO down to fMIN between packets (because there are no EDGE pulses). As the VCO control voltage falls, Q6 base/collector junction becomes forward biased and it saturates. Q5/Q6 base biasing needs to be pretty stiff because it must source 3mA without droop. 

I thought it wise to buffer the loop filter with a JFET source-follower. The VCO control line needs to be driven from a fairly low impedance. The source resistor was returned to a negative supply to keep ID fairly constant and the junction reverse-biased over a wide range of VCO control voltages, however, the circuit seems to work fine if it’s simply returned to ground.

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