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Advanced Low Voltage CMOS with Bus Hold (ALVCH) 3.3V Logic

Advanced Low Voltage CMOS with Bus Hold (ALVCH) 3.3V Logic

Pericom’s new Advanced Low Voltage CMOS with bus hold (ALVCH) logic was especially designed for fast 3.5 ns propagation delays and low noise while providing a “last state” hold feature. This note includes the major advantages of this new product line.

The figure shows a cross section of the ALVCH chip. The inherent diodes D1, D2, and D3 can cause problems in some applications if not for proper chip design methods. R1, R2, and the edge control circuit slow the output rise and fall times. Slowing the edges reduces overshoot and undershoot.


Inherent diode D2 is shorted and the substrate diode D3 is always back-biased. D1 is the only forward biased inherent diode when driving a 5V bus (and this can be alleviated with the I/O Tolerant part). So, there is never a clamp action that could damage the part. The Advanced Low Voltage CMOS family with bus hold, known as AL VCH, has a hold feature that retains the last state at the input.