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FISHINO becomes Mega

FISHINO becomes Mega

SPI interface

Level converters

Even this section turns out to be practically identical to the one seen in Fishino UNO; it is used in order to adjust the ATMEGA’s 5V logic levels to the 3.3V ones of the WiFi module and of the microSD card. The conversion is simply carried out by means of resistive voltage dividers (resistors from R22 to R31) in the 5V -> 3.3V direction, while in the opposite direction we take advantage of the fact that the 5V logics accept high values (well below 3V) as signals, thus proving to be compatible with the 3.3V logics. The MISO (Master In Slave Out) signal should not require an adjustment, in theory, given that the direction goes from the 3.3V logic to the 5V one; we inserted it anyway, in anticipation of the future firmware’s extension of the WiFi module, that will enable the loading of the sketches by means of the same, which requires a roles exchange, therefore in that case the WiFi module becomes the master and the ATmega becomes the slave.

 

MicroSD card interface

The interface is the same we described for Fishino UNO, and reflects the SD shield (or similar combinations); it operates by means of the SPI lines, among which the MOSI (data from the ATmega to the SD, Master Out Slave In), the MISO (data from the SD to the ATmega, Master In Slave Out) and the SCK (clock). The values going towards the SD card are obviously reduced by the level converters of the previous paragraph.

The card selection is carried out by means of the SDCS line, that is active at a low level. In this case the level conversion is carried out by means of a resistor (R23) towards the positive and a diode (D9), that enables the passage of the negative currents only.

The diagram that has been chosen allows to have a standby card, when the SDCS signal (that is connected to Fishino MEGA’s digital pin 4) is not used; with the pin in the three state mode (that is to say, at high impedance) the diode does not conduct and on the SDCS input there is a high value that deactivates the board. The interface is a totally compatible one with the Arduino shields, therefore it uses the same libraries that are used for its functioning, as it will be possible to see in the examples later shown.



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WiFi section

Even the WiFi module has remained unchanged with respect to the one in the Fishino UNO board.

Therefore we will only report some important notes, that is to say the kind of communication with the ATmega, that is carried out via SPI interface and thanks to a firmware we purposely developed and to some circuital gimmicks, such as the D10 diode that is used in order to force the module’s GPIO15 pin to the reset at a low level; without it the module itself would be booted in the “Loading from SD” mode, thus making it unusable. This turns out to be needed, since the GPIO15 line also has a module’s Slave Select (SS) function and therefore it cannot be directly connected to ground.

All the module’s useful pins are brought on a connector (ESPCONN), as reported here as follows.

  • GPIO0: in addition to being usable as a digital input/output, it is needed in order to select the starting mode, when booting the module. The latter may in fact be started from an internal Flash memory (normal functioning, GPIO0 set to 1) or from a serial interface, which is used for the firmware’s reprogramming (GPIO0 set to 0).
  • GPIO2, GPIO4 and GPIO5 are available for the usage as digital pins, and it is possible to take advantage of them by means of the dedicated library functions, as if they were extensions of Arduino’s digital pins.

Rx and Tx compose the module’s hardware serial port and are also used in the firmware’s programming phase. A future firmware extension, that will enable its use as an additional serial port that will allow Fishino MEGA to have a further serial port.

  • CH_PD is the module enabling pin. By bringing it to high level, the module turns out to be enabled (default settings), while a low level puts the ESP in standby mode, thus reducing its consumption to almost zero.
  • RESET is ESP’s hardware reset, which is active at a low level.
  • ADC is ESP’s analog input, that is directed towards a 10 bit A/D (1,024 possible values).

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