Power supply scheme
By now I’m used to FPGAs being a pain in the power supply department and the Virtex-E is no exception. I want to power my board from the now ubiquitous USB connector. Low power designs can be powered directly from a computer port and high power designs from one of those 2A wall chargers. The Virtex-E needs two supplies which makes it less of a pain than the Spartan 3 but it makes up for that in the demands that it can make on the current.
The core supply (VCCINT) required by the Virtex-E family is 1.8V which improves on the 2.5V required by the normal Virtex by reducing power consumption and therefore the heat dissipation. I googled a bit and discoverd SLVA086, a paper from TI that gives typical expected VCCINT power consumption for a fairly heavily loaded design. 1.4A was their worst-case.
Clearly I’d need a switching buck regulator to cover this worst case and the part that I selected was a TI TPS54339DDA. This part can handle up to 3A but the limiting component in my design is the inductor on the output that has a 2.1A DC saturation current.
The other supply required by the FPGA is the supply to the I/O buffers (VCCIO) and this one is typically selected to match the requirements of the external peripherals that you’ll need to talk to. I’ve selected 3.3V as the VCCIO level and, referring back to TI’s helpful analysis I can see that the current demands are, as you might expect, very much lower.
Despite the low demands I’m going with a switcher again. This time it’s one that I’ve used many times before, the LMR10515, again from TI. This is another one that requires few external components and is very simple to use. If you ever need a simple switcher that can drop 5V down to 3.3, 2.8 or any of the other common core supply voltages then I can highly recommend this one.
Decoupling an FPGA is always fun. Just look underneath a busy FPGA on a system board to see what I mean. Ideal decoupling depends entirely on the switching needs of your design which of course isn’t possible to know up front on a development board. Xilinx do publish guidance in XAPP623 based on ascending capacitor decades and a table of percentage weights given to each decade that allow you to figure out how many of each you should select. I used this guide as a reference and selected proportions of 47n, 470n and 2.2µ ceramic capacitors. Bulk capacitance is supplied by a pair of 470µ electrolytics, one each on the 1.8V and 3.3V supplies.
