Altera® Stratix V® FPGAs offer up to 66 transceiver channels per device for fast data rates to meet increasing system bandwidth demands. As a result of the high transceiver count, board designers may find it difficult to route all the channels while keeping control of the board cost. This application note compares several serial channel breakout routing techniques to help you meet 10 Gbps to 28 Gbps data rate channel performance while balancing the performance versus cost trade-offs. Specifically, the channel breakout underneath the ball-grid array (BGA) has an impact on the board signal integrity and cost.
This application note discusses how to appropriately design the channel breakout in the BGA via field region while reducing PCB cost. Detailed layout design examples and simulation results are presented to compare the performance of the routing topologies. Simulation results of insertion loss, return loss, and crosstalk performance are compared to demonstrate the impact of the different breakout routing schemes.
