WireFrame FPGA Board, Validating counter modules with ModelSim Tutorial

this article is second part of creating  your first design with FPGA and verilogHDL, in particular WireFrame FGPA Board Xilinx XC3S250E board.

have created and implemented a basic counter module so that we can blink few leds. now we will verify that counter module with the help of a test-bench module and Altera ModelSim Software, there are many software which you can you to simulate your design none of the component we use are platform dependent.

so lets start , first of all we are going to need a testbench module , testbench module is nothing but a simple verilog module which feeds the inputs to our counter module , monitor the output and ultimately validates that the under test module is working as it should be, to achieve this testbench modules have few extra features or you can call them have extra powers , like you can specify initialization block  and specify time when a instruction will execute due to testbench module never ever get synthesize  , they just run in the simulation software that is all.

lets start writing a test bench ,

1. you need a module ,
2. few reg and wire declaration  for ports of the module under test,
3. an instance of the module inter test,
4. and  a initial block to do one time events,
5. and finally a always block to generate clock for the module under test.

`timescale 1ns/1ps  // simmulation happen in picosecond time base ,                     // we have up scaled it it to ns                      // when we say #5 it will mean 5 ns , and when we say #1000 it will 1000ns, 1us module counter_testbench(); Advertisement reg clock_tb,reset;       //mapped with ports of the module under test  wire [32:0]out_tb; counter t0(reset,clock_tb,out_tb);  //create an instance of the counter module which is under test    initial    begin  $monitor(“%g,out_tb=%d,reset=%b”,$time,out_tb,reset); // these values will be visible in the transcript window at the bottom clock_tb=0; reset=1;  //enable the counter module ,reset is active low input #100      // right here we should have (200/5)/2 = 20 in the cout output  value reset=0; //reset the timer module for a while #300 reset=1; #1000 $stop(); // right here we will have (1000/5)2=100 in the count output end   always #5 clock_tb=~clock_tb;  //generate clock by toggling Clock line ever 5 unit of time endmodule