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Die photos and analysis of the revolutionary 8008 microprocessor, 45 years old

Die photos and analysis of the revolutionary 8008 microprocessor, 45 years old

The register file

To show what the chip looks like in detail, I’ve zoomed in on the 8008’s register file in the photo below.
The register file consists of an 8 by 7 grid of dynamic RAM (DRAM) storage cells, each using three transistors to hold one bit.8
(You can see the transistors as the small rectangles where the orange polysilicon takes on a slightly more vivid color.)
Each row is one of the 8008’s seven 8-bit registers (A, B, C, D, E, H, L).
On the left, you can see seven pairs of horizontal wires: the read select and write select lines for each register. At the top, you can see eight vertical wires to read or write the contents of each bit, along with 5 thicker wires to supply Vcc.
Using DRAM for registers (rather than the more common static latches) is an interesting choice.
Since Intel was primary a memory company at the time, I expect they chose DRAM due to their expertise in the area.

The register file in the 8008. The chip has seven 8-bit registers: A, B, C, D, E, H, L

The register file in the 8008. The chip has seven 8-bit registers: A, B, C, D, E, H, L

How PMOS works

The 8008 uses PMOS transistors.
To simplify slightly, you can think of a PMOS transistor as a switch between two silicon wires, controlled by a gate input (of polysilicon). The switch closes when its gate input is low and it can pull its output high.
If you’re familiar with the NMOS transistors used in microprocessors like the 6502, PMOS may be a bit confusing because everything is backwards.



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A simple PMOS NAND gate can be constructed as shown below.
When both inputs are high, the transistors are off and the resistor pulls the output low.
When any input is high, the transistor will conduct, connecting the output to +5.
Thus, the circuit implements a NAND gate.
For compatibility with 5-volt TTL circuits, the PMOS gate (and thus the 8008) is powered with unusual voltages: -9V and +5V.

A NAND gate implemented with PMOS logic.

A NAND gate implemented with PMOS logic.

For technical reasons, the resistor is actually implemented with a transistor. The diagram below shows how the transistor is wired to act as a pull-down resistor. The detail on the right shows how this circuit appears on the chip. The -9V metal wire is at the top, the transistor is in the middle, and the output is the silicon wire at the bottom.

In PMOS, a pull-down resistor (left) is implemented with a transistor (center). The photo on the right shows an actual pull-down in the 8008 microprocessor.

In PMOS, a pull-down resistor (left) is implemented with a transistor (center). The photo on the right shows an actual pull-down in the 8008 microprocessor.

 


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