Notes and references
[1] While a typical PLA acts as structured logic gates generating signals (as in the Z-80 or 6502), the ARM1’s PLA is different. Exactly one row is active at a time, so the PLA functions more like a ROM. There’s a discussion of ROMs as PLAs in section 7.3.2.2 of The Architecture of Microprocessors.[2] My explanation of the LDR instruction is simplified, since the instruction provides a variety of addressing mechanisms. It also provides byte access as well as 32-bit word access. Full details are here.
[3] IBM’s ROMP microprocessor is generally considered RISC, but uses a 256×34 control ROM. Likewise, the Intel i960 is usually considered RISC but uses microcode.
[4] ARM1 designer Furber’s book VLSI RISC Architecture and Organization discusses the ARM1 and other RISC chips. Section 1.3.1 has an extensive discussion of microcode. He describes how the ARM1’s block move and ARM2’s multiplication operations are under the control of a separate hardware unit inside the chip, unlike how a microcoded implementation would operate. Section 4.7 describes the ARM1’s control logic.
Content retrieved from: Original article by Ken Shirriff at his Blog.
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