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The ARM1 processor’s flags, reverse engineered

The ARM1 processor’s flags, reverse engineered

Updating the condition flags with results of an operation

One feature that distinguishes the ARM processor from most other processors is that condition flag updates are optional. If an arithmetic operation has the S bit (bit 20) set, the flags are updated, otherwise they are not.
By looking at how the aluflag control signal is generated, we can see how this functionality is implemented.

The ARM manual explains how flags are updated by a data processing instruction (ADD, etc.)

The ARM manual explains how flags are updated by a data processing instruction (ADD, etc.)

If the aluflag control signal[4] is high, the multiplexer on the right will select the flag value generated by the ALU, rather than the recirculated value.
The aluflag control signal is activated if
pla1_aluproc
from the instruction decoder is set
(details)
and if the S bit (bit 20) is set in the instruction register.
The pla1_aluproc line is set when the ALU is doing a data processing operation, but not when the ALU is, for example, computing an address offset.
This is why the condition flags are updated only for relevant operations.
If an abort of the instruction occurs, aluflag is blocked, preventing the flags from being modified.



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Arithmetic versus logic operations

The following text from the
ARM databook explains the behavior of the condition flags during a data processing (ALU) operation. The part of interest is that
the carry (C) and overflow (V) flags are treated differently for logical operations versus arithmetic operations.

The ARM manual explains how arithmetic and logic operations update the flags differently.

The ARM manual explains how arithmetic and logic operations update the flags differently.

The schematic shows the circuits that explain this behavior.
The control line pla1_aluarith is generated by the instruction decode logic
(details);
it is high if the ALU operation is an arithmetic operation (e.g. ADD), and low for a logic operation (e.g. AND).
This control line selects the different C and V inputs for arithmetic or logical operations.
For the C flag, this control line selects between the ALU’s carry out and the shifter’s carry out. (The shifter has a lot of logic because the carry out depends on the type and direction of shifting.)
For the V flag, this control line selects between the ALU’s overflow signal and the old V flag — this is why logic operations don’t update the V flag.

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