Browse over 10,000 Electronics Projects

The ARM1 processor’s flags, reverse engineered

The ARM1 processor’s flags, reverse engineered

Writing the flags directly

As described earlier, the flags and the Program Counter share register R15, so storing a value in R15 can update the flags.
This is implemented through the multiplexer on the left.
If control signal writeflags is activated, the multiplexer on the left will select the value from the ALU bus, rather than the recirculated value, updating the flags with the new value. Otherwise, nowriteflags is activated, selecting the recirculated value and leaving the flag unchanged.
(Note that both writeflags and nowriteflags are inactive during clock phase Φ1, effectively disconnecting the multiplexer output.)

The generation of writeflags is relatively complicated.
First, if pla_psrw
this indicates a block copy instruction (LDM/STM) is writing to the PSR;
if instruction register bit 22 (S) is set the flags will be updated.
Second, aluflag (described above) indicates an ALU data processing operation should update the flags.
In either of these cases, as long as abort is clear, and wpc (write PC) is set, then the nowriteflags1 signal is active. This signal is combined
with the clock Φ2 to generate the writeflags and opposite nowriteflags signals sent to the multiplexer.
This implements the logic described on page 2-34 for data processing instructions:



Advertisement1


The ARM manual explains how flags are updated by the LDM block transfer instruction.

The ARM manual explains how flags are updated by the LDM block transfer instruction.

Pages: 1 2 3 4 5 6 7 8 9 10 11

 


Top