Looking at the block diagram of the ARM1 process explains some of the behavior when reading the flags.
A data processing instruction specifies three registers: the operation is performed on the first two registers and the result stored in the third.
The first register (Rn) is read over the A bus. The second register (Rm) is read over the B
bus and goes through the barrel shifter. The ALU generates the result of the operation,
which is stored to a third register (Rd) via the ALU bus.
The block diagram above shows how the flags are connected to the chip’s buses.
The flags are separate from the register file; they are written via the ALU bus and read via the B bus. Thus, the flag value in R15 can only be accessed as the second register (Rm) via the B bus, and not as the first register (Rn) via the A bus. This explains the behavior described in the manual:
The process to write data to the B bus may seem backwards.
The B bus is complemented, so a 1 on the bus indicates a 0 value.
In more detail, the B bus is pulled high in clock phase Φ2 by transistors on the right of the register file (details). In clock phase Φ1, anyone writing to the bus sends a 1 by pulling the corresponding bus line low.[5]
From the schematic, you can see that the control signal psr_oen (PSR output enable) controls putting the (complemented) flag values on the B bus.
If psr_oen is active (only in phase Φ1) and the flag value is 1, the output transistors will pull the bus to 0.
The psr_oen signal is enabled to read the flags in two cases.
The first happens when flags are being saved to R14 for a trap.
The pla2_psren (PSR enable) signal controls this;
it comes from instruction decoding at the start of a software interrupt (SWI), coprocessor instruction (i.e undefined instruction), or interrupt.
The second case is when the R15 is being read via the B bus. This is indicated when pla2_ben (B Enable) and bpc (B bus PC) are active.
The pla2_ben signal (PSR enable) comes from instruction decoding and is enabled at some point during most instructions.
The register file generates the bpc signal when the B bus accesses the PC.