Browse over 10,000 Electronics Projects using the Page Numbering provided at the bottom of each Page.

General Guidelines & Procedures for Using the HMC661LC4B with an ADC

General Guidelines & Procedures for Using the HMC661LC4B with an ADC

Wideband data acquisition systems with multi-GHz bandwidth are needed for a variety of applications such as software defined radio, radar systems, electronic warfare (EW)/electronic intelligence (ELINT), and test and measurement equipment. Ideally, system designers would like to be able to connect the signal source (for example an antenna) directly to a wideband, high dynamic range Analog-to-Digital Converter (ADC) for digitization. Many of these applications involve sub-sampling where the signal of interest is a high frequency signal well beyond the ADC sample rate. A key limitation to this approach is that current ADCs do not usually have sufficient bandwidth for these very wideband applications. Although several high speed ADCs offer enhanced sample rates, few of them offer input bandwidth beyond a few GHz. In addition, maintenance of good sampling linearity at frequencies above the UHF band is technologically challenging and most current ADCs suffer rapidly degrading linearity above 1 or 2 GHz signal frequency.

These limitations can be overcome using the HMC661LC4B Ultra Wideband Track-and-Hold Amplifier (THA) which is designed for use in microwave data conversion applications requiring maximum sampling bandwidth, high linearity over a wide bandwidth, and low noise. The HMC661LC4B, which offers 18 GHz input bandwidth and excellent broadband linearity, is used as an external master sampler at the front end of the ADC. Once extended bandwidth sampling takes place within the HMC661LC4B, the low bandwidth held output waveform can by processed by an ADC with substantially reduced bandwidth. ADC linearity limitations at high input frequencies are also mitigated because the settled THA waveform is processed with the optimal baseband linearity of the ADC. Additionally, the HMC661LC4B offers very low random sample jitter of <70 fs which minimizes jitter induced signal-to-noise (S/N) ratio degradation at high microwave signal frequencies. This jitter is significantly better than that typically obtained from currently available ADCs. The result is a radical extension in input bandwidth, substantial improvement in high frequency linearity, and improved high frequency S/N ratio for the THAADC assembly compared to the performance of the ADC alone.

This application note provides guidelines for using the HMC661LC4B with high speed ADCs to enhance their bandwidth and high frequency performance. An overview of THA operation and general operating recommendations for maximizing device performance are described. The setup and timing adjustment of a typical evaluation board – based breadboard assembly incorporating the HMC661LC4B as a master sampler for high speed ADCs is also provided. Examples of the performance that can be obtained when the HMC661LC4B is used in an evaluation board setup with some current high speed ADCs may be found in the companion Hittite application note: Bandwidth & Performance Improvements of High Speed A/D Converters Using the HMC661LC4B.