This application note details the difference between DS75 communication timing and the I²C specification. Under I²C, the SCL and SDA lines are allowed to transition simultaneously because SDA is delayed internally by the slave device for at least 300ns. The DS75 does not delay the SDA signal with respect to SCL therefore SDA must be held in the proper logic state by the bus master until SCL has fully transitioned to logic low to prevent false generation of START or STOP operations.
The DS75's SDA line does not have an internal delay relative to SCL. For this reason the SDA logic level must be held external to the DS75 until SCL has transitioned to logic low when writing data; otherwise a start or stop condition may be recognized instead. When writing a logic "1" on the 2-wire bus, SCL must reach the guaranteed logic low threshold VIL (0.3 x VDD maximum) before SDA transitions below the guaranteed logic high threshold VIH (0.7 x VDD minimum). When writing a logic "0", SCL must reach VIL before SDA transitions above VIL. When generating a START condition, SDA must reach VIL before SCL transitions below VIH. When generating a STOP condition, SDA must reach VIH before SCL transitions below VIH. Both VIL and VIH levels are production tested on each device. This guarantees proper operation using this timing over the full voltage and temperature ranges including device fabrication tolerances.