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Altera PHYLite for Parallel Interfaces Loopback

Altera PHYLite for Parallel Interfaces Loopback

This application note showcases loopback reference designs using the Altera PHYLite IP core.

This document is divided into three segments:

  1. A simple input/output PHYLite simulation reference design.
  2. A simple input/output PHYLite with dynamic reconfiguration using Arria 10 devices hardware reference design.
  3. Functional description for the modules and application used in both reference designs.

The simulation reference design is a simple design that simulates the behavior of the Altera PHYLite IP core. This design consists of 2 main components:

  • A device Under Test (DUT) module that includes two Altera PHYLite IP instances.
  • A traffic generator module