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15-25 MHz Fractional-N Synthesizer

15-25 MHz Fractional-N Synthesizer

This fractional-N synthesizer covers 15 to 25 MHz in 1 Hz steps. Most of the work is done by the 128-macrocell CPLD which hosts the reference and VCO dividers.
Another objective for this project was to evaluate the AD9901 type dead-band-free phase-frequency detector (PFD) as recommended by Oleg Skydan[1]. This becomes an XOR-gate type phase detector once the signals are close in frequency. It has no cross-over region, and is therefore highly linear around zero phase error. The action of the MASH produces predominently high frequency noise at the PFD output, which is removed by the loop filter. Any non-linearity in the PFD could produce low-frequency intermodulation products which would not be removed. 

A third objective was to try a full 32-bit fourth-order MASH. Previously, despite using a larger CPLD, I only managed to squeeze-in a 16-bit MASH. This time, with a higher output frequency, and more clock cycles to play with, it was possible to serialise the MASH processing. Obviously, I had to take the storage off-chip: four 32-bit accumulators alone would use up 128 macrocells! The idea of using stored program control evolved from this requirement. The embedded CPU has 7 unconditional instructions. 

Perhaps this project’s most novel feature is the use of JamTM Standard Test and Programming Language (STAPL) to download stored program and initial MASH starting values into the attached SRAM: there are few examples of Jam STAPL on the web. Intended for in-circuit testing, it permits direct (albeit slow) access to CPLD I/O pins from the PC. The entire boundary scan register (288-bit for EPM7128) is serially loaded.

Article by Andrew Holme at http://www.holmea.demon.co.uk/

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