This digital echo unit resulted from a discussion with a friend who is a member of a local amateur dramatic group. Until now they had been producing echo sound manually by tape recording the same sound several times at lower recording levels – I admire their patience.
Although this method worked OK for longer echoes on single sounds, it could not be used to add a short reverberation on speech.
An exact specification was not offered, they felt that almost anything would be better than the existing system. We decided that about half a second between echoes would be more than adequate for a maximum delay range. The shortest delay is so fast that sounds resembling microphone feedback can be obtained. Metallic alien reverberations similar to those on the “Smash” instant potato television adverts are also possible.
Simplicity of operation is essential for the intended use. Consequently, there are only three controls on the front panel. Two of these set the delay required (coarse and fine). The third is the Repeat control, which sets the amount of echo signal fed back around the loop. This ranges from 0% to almost 100%.
My original plan was to use bucket brigade delay line chips, however several devices would have been necessary to cover the required delay at a reasonable frequency bandwidth. Significant distortion can also result as the voltage samples are passed down the chain.
The design presented here uses an 8K RAM chip to store the data samples. The delay of half a second is achievable, with a bandwidth of 8KHz. The incoming signal passes through with no bandwidth limiting. Distortion on the echo signals is generally less than 5%, although this will build up each time a sound is echoed.
The upper frequencies would normally be lost on natural echos, so the bandwidth limitation is not a problem in practice. Similarly the distortion on the echo signals will generally pass unnoticed.
The complete circuit diagram appears in figures ** and **.
Starting with the digital section. IC1 is the clock generator, which runs at four times the sampling frequency. The frequency is adjustable over a limited range by VR1, the Delay Fine control. This slightly unusual configuration gives an output with an approximately equal mark-space ratio.
The A-D convertor IC7, requires a negative bias on pin five. Since the current required in minimal, this negative voltage is obtained by rectifying the clock signal from IC1, giving approximately -4V.
IC2 produces the four timing pulses required, three of which are inverted by gates in IC3. When Q1 goes high, the A-D convertor IC7 starts a conversion. When Q2 is high, the data in the RAM is sent to the D-A convertor IC8, which produces the appropriate voltage. When Q3 is high, the data from the A-D is stored in RAM. Finally when Q4 pulses high, the address counters IC4 and IC5 are incremented.
SW2 (Delay Coarse) sets the count reached by the address counters before they are reset. This sets the amount of the RAM chip to be used.
Ideally I would have had just one continuously variable delay pot, on the 555 clock circuit. However, it was not possible to achieve the required range with a respectable frequency response due to the A-D conversion time.
Visit Here for more.