74HC74 dual D flip-flop: pinout, PRE and CLR, divide-by-2 speed and a push-button toggle

With PRE and CLR both high, the flip-flop does one thing: on each rising clock edge, Q takes the level on D and /Q takes the opposite. Between edges, D can do what it likes. Pull PRE low and Q goes high straight away; pull CLR low and Q goes low.

With PRE and CLR both low, Q and /Q both go high, which is not a real state. TI notes it does not persist: whichever pin is released last decides where Q ends up, and if both are released together you cannot know. Never drive both at once on purpose.

The output limit is 25 mA per pin and 50 mA through VCC or ground for the whole chip. That is enough for an indicator LED on each output at a few milliamps, but these are logic outputs, and TI writes its output figures at 4 mA.

The input thresholds are 0.7 and 0.3 of VCC at both supplies TI lists, so on 5 V a high must be at least 3.5 V and a low at most 1.5 V. A 3.3 V controller's high falls 0.2 V short; the HCT74 in the substitutes table fixes that.

D has to be steady for a setup time before the rising edge: 25 ns at 4.5 V up to 85 °C (20 ns at 25 °C). The hold time is 0 ns, so D may change the moment the edge has passed. Q shows the new value within 44 ns of the edge, measured into a 50 pF load.

The zero hold time is what lets one flip-flop feed another on the same clock: the second one has already taken its D before the first one's Q starts to move. It is also what makes the divide-by-2 below work.

Tie D to /Q and every rising edge flips the output, so Q runs at half the clock. Chain a second flip-flop off the first one's Q and you get a quarter. From a 16 MHz crystal clock, the two outputs give 8 MHz and 4 MHz.

The clock-frequency row allows 16 MHz: it gives 25 MHz up to 85 °C. The loop itself is tighter than that row suggests. After an edge, /Q takes up to 44 ns to change, and it must then sit on D for 25 ns before the next edge.

In practice it works: the 44 ns figure is measured into 50 pF, and /Q here drives one input of at most 10 pF, so the real delay is shorter. But the sheet does not promise it at 85 °C. For a board that has to be sure, run the chip at a supply above 5 V (60 ns at 6 V), or use the 74LVC74A on 3.3 V, which TI rates to 100 MHz. The second stage only sees 8 MHz, so it has plenty of room, and its output settles 88 ns after the input edge, two delays in a row.

TI's application section uses one flip-flop as a toggle switch: D tied to /Q, the button on CLK, so each press flips Q. Two details decide whether it works.

Power-on reset. A flip-flop can wake up either way. TI puts an RC on CLR so Q always starts low: with 10 kΩ to VCC and 1 µF to ground, CLR stays under 1.5 V for 3.57 ms after power-on and passes 3.5 V at 12 ms. The sheet needs only 25 ns of CLR low, so this is generous.

The button needs a Schmitt trigger. A contact bounces, so most builders smooth it with an RC. But a 100 kΩ and 100 nF debounce (10 ms) takes 8.47 ms to cross from 1.5 V to 3.5 V. The HC74's clock input asks for an edge faster than 500 ns, about 16,946 times quicker. A slow edge on a plain CMOS input can oscillate as it crosses the threshold and clock the flip-flop several times per press. TI's text says the same: debounce the switch, then pass it through a Schmitt-trigger buffer such as one gate of a 74HC14 before CLK.

CLR can take the slow RC directly. While it rises, the input may draw extra current for a few milliseconds, but every wobble only clears a flip-flop that is already clear.

Standing still, the chip draws at most 40 µA up to 85 °C. Clocking costs more: each flip-flop has a power dissipation capacitance of 35 pF. One flip-flop clocked at 16 MHz on 5 V draws 35 pF × 5 V × 16 MHz = 2.8 mA, or 14 mW, before the current that charges whatever the outputs drive. Fit 100 nF from VCC to ground right at pin 14, as TI asks.

• Pins 8 and 9 are /2Q then 2Q, the reverse of flip-flop 1's pins 5 and 6. Check them on a new layout.
• Tie PRE and CLR high when unused. Never pull both low together.
• Tie every input of an unused flip-flop to VCC or ground.
• Feed CLK from a clean logic edge. A button or an RC goes through a Schmitt trigger (74HC14) first.
• For divide-by-2, wire D to /Q on the same flip-flop; for divide-by-4, clock the second flip-flop from the first one's Q.
• On 5 V, a 3.3 V controller cannot reliably clock the HC74: it needs 3.5 V. Fit an HCT74.

A 74HC74 from another maker drops into the same socket. The HCT and LVC parts below share the pinout but differ in supply range and input levels; check those first.

1. Wire VCC to pin 14, ground to pin 7, 100 nF across them. Tie /1PRE (pin 4) and /1CLR (pin 1) to VCC.
2. Put an LED and 1 kΩ from 1Q (pin 5) to ground. Tie the second flip-flop's pins 10 to 13 to VCC.
3. Set 1D (pin 2) high, then touch 1CLK (pin 3) from ground to VCC with a wire: the LED lights.
4. Set 1D low and give CLK another rising edge: the LED goes out.
5. Briefly ground /1PRE: the LED lights without any clock. Ground /1CLR: it goes out.

A wire touched by hand bounces like a button, but with D held steady the extra edges change nothing. The switches lesson shows what that bounce looks like, and the logic levels lesson covers the 0.7 and 0.3 VCC thresholds.

Use the SN74HC74N on a 5 V board with 100 nF at pin 14 and every unused input tied to a rail. For a toggle button, follow TI's circuit: RC debounce, a 74HC14 gate, then CLK, with 10 kΩ and 1 µF on CLR for a known start. For clock division up to about 14 MHz the HC74 is guaranteed hot; above that, use the 74LVC74A.

Shops list it as 74HC74 or SN74HC74N in DIP-14, and as 74HC74D for boards. The 74LS74 and 74HCT74 sit on the same shelf and look identical; check the letters after 74. Our guide to buying electronic components in India compares ten online sellers and covers how to spot fakes.