How the ARM1 decoded its instructions

An instruction arriving from memory is only a 32-bit pattern. Nothing in the data path knows what it means. Somebody has to tell the register file which registers to read, tell the ALU whether to add or AND, tell the shifter how far to shift, and decide whether the result is written back and whether the flags change.

That somebody is the control unit, and its output is a bundle of control lines. Some instructions need one clock cycle of control lines. A load needs several, because the chip must first work out an address, then wait for memory, then put the data in a register. So the control unit needs two inputs: which instruction, and which cycle of it we are on.

Microcode. Store the control lines for every step of every instruction in a ROM. The instruction picks a starting address, a small micro-program counter steps through the rows, and each row drives the control lines for one step. Changing an instruction means changing ROM contents rather than logic, which suits a large and irregular instruction set.

Hardwired logic. Build the control lines directly from gates whose inputs are the instruction bits and a cycle counter. It is faster and smaller when the instruction set is simple, and painful when it is not.

A programmable logic array is two grids of transistors. The first grid, the AND plane, has one row per pattern: each row watches some of the input bits and ignores the rest, and goes active only when every bit it watches matches. The second grid, the OR plane, connects each row to the outputs it should drive.

On a chip the pattern is fixed by the masks, so a PLA behaves like a ROM that only has the rows you need. A ROM with 12 address bits must hold 4,096 rows whether you use them or not. A PLA with 12 inputs can have 42, if 42 patterns are all you care about.

If AND and OR built from switches are new to you, the diode logic glossary entry shows the same two operations made from diodes and resistors, and logic families covers the transistor versions.

Sophie Wilson and Steve Furber designed the ARM1 at Acorn in 1985. It had about 25,000 transistors on a 3 micron process, per Shirriff's overview of the chip.

Its instruction decoder is a PLA holding 42 microinstructions of 36 bits each. The rows fall into 18 classes of instruction, one to four rows per class. Only six of the 32 instruction bits take part in choosing the class. The row within the class comes from the cycle number kept by a separate sequence controller, and each row tells that controller what the next cycle number should be.

A load register (LDR) takes three rows, so three cycles: one to compute the address, one to fetch from memory, one to write the register. The block transfers LDM and STM reuse a row in a loop, once per register moved, and can take up to 17 cycles.

The 36 output bits are not the final control lines. Hardwired logic after the PLA reads other instruction bits to pick the actual register, the ALU operation and the shift, and a separate circuit checks the condition field. Dave Mugridge's write-ups of the ALU control and shifter decoding show those second-level circuits.

That split is why the label is argued over. RISC chips are not supposed to be microcoded, and Shirriff notes that the designers themselves described a two-level decode rather than microcode. His own verdict is "partially microcoded", or hybrid microcode and hardwired control.

Shirriff gives the sizes. The ARM1 table is 1,512 bits. The 8086 used 504 microinstructions of 21 bits, 10,584 bits. The 68000 had 544 words of 17-bit microcode feeding 366 words of 68-bit nanocode, 34,136 bits in all.

The gap comes from the instruction set. Every ARM1 instruction is 32 bits with its fields in fixed places, only the load and store instructions touch memory, and simple instructions finish in a single cycle. There is little left for a sequencer to do, so the table stays small. The 8086 and 68000 had variable-length instructions and memory operands on arithmetic, and each of those needs its own run of steps.

The Visual 6502 team's ARM1 simulator runs in a browser and is what Shirriff used for his analysis, so you can follow the same chip he did. His follow-up on instruction sequencing compares the ARM1's sequence controller with the 6502 and Z-80.

The PLA, the counter and the control lines rest on a few basics we teach.

• Analog vs digitalWhy a processor treats every wire as a 1 or a 0.
• Logic levelsWhat voltage counts as a 1 on a control line.
• Logic familiesThe gates a PLA's AND and OR planes are made of.
• The MOSFET as a switchEvery cell in the PLA grid is a transistor used this way.
• The integrated circuitHow 25,000 transistors end up on one die.
• 8051 pin diagramAn 8-bit microcontroller from the same decade, pin by pin.

• Ken Shirriff, Reverse engineering the ARM1 processor's microinstructions, righto.com, February 2016. The decode PLA size, classes, rows per instruction, LDR and LDM/STM cycle counts, the 8086 and 68000 sizes, and the "partially microcoded" verdict.
• Ken Shirriff, Reverse engineering the ARM1, ancestor of the iPhone's processor, righto.com, December 2015. Designers, year, transistor count and process.
• Ken Shirriff, Reverse engineering ARM1 instruction sequencing, compared with the Z-80 and 6502, righto.com, February 2016. The sequence controller, how it picks the next cycle, and single-cycle simple instructions.
• Dave Mugridge, Inside the ARMv1: the ALU control logic and decoding barrel-shifter commands, January 2016.
• Visual ARM1 simulator, visual6502.org.

All links checked 30 September 2026.