How to design a great PCB: the layout rules, with the numbers

Before you draw a trace, set the design rules in your CAD tool, because they decide everything after. A low-cost Chinese prototype service such as JLCPCB states 0.1 mm trace and space on one- and two-layer boards and 0.09 mm on multilayer, a 0.15 mm minimum via hole and a 0.25 mm minimum via pad (JLCPCB PCB manufacturing capabilities). Silkscreen lines must be at least 0.15 mm and text at least 1 mm tall, or it smudges.

Treat those as limits. We set our rules at 0.15 mm trace and space, a 0.3 mm via drill and a 0.6 mm via pad. That gives the fab room to be slightly off and lets any other supplier make the same board. Go finer only where a part forces it, such as a 0.5 mm pitch QFN.

Our take: set the rules from the fab's page, then design one step coarser. A board that only one factory can make on a good day is a bad design.

A two-layer board is cheap and fine for a power supply, a relay board or a slow microcontroller project. Its weakness is distance. If you flood the bottom with ground, that ground is 1.53 mm below the top traces, and a fast signal's behaviour depends on how far away its return is.

Figure 1 shows the effect. A 50 Ω trace, the impedance an RF connector or antenna expects, comes out 2.88 mm wide on a two-layer board (E. Hammerstad and Ø. Jensen). That is wider than most IC pins. On a four-layer board with the ground plane 0.20 mm under the top layer, it is 0.38 mm, which an ordinary trace can be. Turn it around: a plain 0.25 mm trace is about 135 Ω on the two-layer board and 63 Ω on the four-layer one. The closer the plane, the closer an ordinary trace comes to 50 Ω.

A good four-layer stackup is signal, ground, power, signal. The plane right under the top layer is ground, unbroken. The impedance matching lesson covers why 50 Ω matters once a trace gets long compared with the signal's rise time.

Our take: use four layers when the board has USB, Ethernet, a radio module, a switching regulator above about 1 MHz or a fast clock. The price gap with two layers is small for prototypes (check your fab's calculator); the EMC and debugging gap is not.

Routing is easy on a well-placed board and painful on a badly placed one, so spend the time here. Our order:

1. Fixed parts. Connectors, switches, LEDs that show through a case, mounting holes. The enclosure decides where these go, not you.
2. The main IC, then its partners. Put the microcontroller where its busiest pins face the parts they talk to: the crystal, the USB connector, the sensor.
3. Power. Keep the regulator near where the power comes in, and keep a switching regulator's loop (input capacitor, switch, diode or low-side FET) as tight as the datasheet layout shows. The regulator thermal design lesson covers the copper a linear regulator needs to stay cool.
4. Decoupling capacitors, at the pins. Each one goes beside the power pin it serves, on the same side of the board. The next section shows why.
5. Everything else. Pull-ups, LEDs and their resistors fill in around the rest.

Keep noisy and quiet parts apart: the switching regulator and the relay at one end, the analogue input and the crystal at the other. The EMI and EMC basics lesson explains what couples where.

A decoupling capacitor supplies the sudden current an IC draws on each clock edge. At those speeds a capacitor stops acting as a capacitor. A 100 nF part with 1 nH of mounting inductance resonates at 15.9 MHz; above that it is an inductor, and its impedance rises with frequency.

The trace to the pin adds more inductance. Rosa's formula for a straight bar (E. B. Rosa) gives a 0.25 mm, 10 mm trace about 9.5 nH, close to the old 1 nH per mm rule of thumb. At 100 MHz, the capacitor at the pin is 0.61 Ω. Move it 5 mm away and it is 3.2 Ω; 10 mm, 6.6 Ω; 20 mm, 14.3 Ω. A capacitor at the far end of the board is barely connected.

These are the inductances of an isolated trace. Over a solid plane the loop is smaller and the figures drop, but the ranking stays the same. So the fix is placement. Changing 100 nF to 1 µF does almost nothing at 100 MHz, where the inductance sets the impedance. The decoupling capacitors and IC power decoupling lessons go deeper, including why several values in parallel can help.

Our take: put the capacitor pad within 2 mm of the power pin, with its ground side going straight down a via to the plane. If that means the capacitor sits on the other side of the board, a via each side is still better than 10 mm of trace.

A trace heats because it has resistance. One-ounce copper is 0.035 mm (35 µm) thick, and copper's standard resistivity is 0.017241 Ω·mm²/m at 20 °C (NBS Handbook 100), so every square of 1 oz copper is 0.49 mΩ, whatever its size. A trace 0.25 mm wide and 50 mm long is 200 squares, about 99 mΩ.

The usual sizing rule comes from IPC-2221: I = k × ΔT^0.44 × A^0.725, with A the copper cross-section in square mils and k = 0.048 for an outer layer or 0.024 for an inner one (IPC-2221B). Solved for width with 1 oz copper and a 10 °C rise:

Two cautions. The inner-layer column is conservative: the newer IPC-2152 measurements found that inner traces run cooler than the old chart assumes, since the board spreads the heat (IPC-2152). And temperature is not the only limit. Voltage drop often bites first.

Worked example. A 5 V rail carries 2 A for 50 mm on the 0.78 mm the table gives. At 10 °C above room temperature that trace is 32.8 mΩ, so the load sees 66 mV less and the trace burns 131 mW. Fine. Route the same current down a 0.25 mm signal trace and you lose 197 mV, which can be enough to reset a 3.3 V regulator working near its dropout. The wire resistance and voltage drop lesson works the same sum for cables.

Our take: size power traces for drop, not just for heat. Work out the millivolts your load can lose and pick the width that stays under it; a copper pour is often simpler than a wide trace.

A via is a short copper tube. Take a 0.3 mm drill through a 1.6 mm board with JLCPCB's stated average plating of 18 µm (JLCPCB PCB manufacturing capabilities). The copper ring has a cross-section of 0.0159 mm², so the via is about 1.7 mΩ. Treating that ring like an outer trace in the IPC-2221 formula gives about 1.4 A for a 10 °C rise.

So a 3 A path changing layers needs 3 vias, and we would use 4 for margin. Spread them across the trace width rather than in a line along it, so the current shares them. Plating thickness varies from hole to hole, which is another reason to never rely on a single via for power.

Current flows in loops. On a board with a solid ground plane, the return current of a fast signal flows in the plane directly under its trace, because that is the path of least inductance. Keep that path whole and most of the trouble never starts.

• Do not cut the plane under a signal. A slot forces the return current around it, which turns a small loop into a large one. Large loops radiate and pick up noise.
• Change layers next to a ground via. When a fast signal goes through a via to the other side, its return has to change planes too. Put a ground via beside it.
• Do not split ground into analogue and digital islands unless a datasheet tells you to. One plane, with the parts placed so the noisy currents never cross the quiet area, works better on most boards. The ground loops lesson shows what goes wrong with multiple paths.
• Keep sensitive traces away from the board edge and away from switching nodes; a few millimetres of plane beside them helps.

• Run the design-rule check with your fab's numbers loaded. Zero errors, and read every warning.
• Print the board at 1:1 on paper and set the real parts on it. Footprint mistakes show at once.
• Check every polarised part: diodes, electrolytics, LEDs, and pin 1 on each IC.
• Label connectors, test points and the board revision in silkscreen.
• Add test points for each supply rail and ground; a probe clip needs somewhere to go.
• Open the Gerbers in a separate viewer before uploading. What the viewer shows is what the fab will make.

Once it is built, the soldering basics lesson covers assembly, and our PCB Analyzer page tracks the layout checker we are building.

• Decoupling capacitorsValues, placement and why Figure 2 looks the way it does.
• IC power decouplingSupplying the current an IC draws on each clock edge.
• Wire resistance and voltage dropThe millivolts behind the trace-width example.
• Resistivity and conductanceWhere 0.017241 Ω·mm²/m comes from.
• InductanceWhy a short trace has nanohenries, and why they matter.
• Impedance matchingWhen a trace needs to be 50 Ω.
• EMI and EMC basicsLoops, planes and what radiates.
• Skin effectWhy copper resistance rises at high frequency.

• IPC-2221B, Generic Standard on Printed Board Design, §6.2 and §10.1.1 (table of contents) (the conductor current chart behind I = k·ΔT^0.44·A^0.725, k = 0.048 outer layers, 0.024 inner layers, A in square mils)
• IPC-2152, Standard for Determining Current Carrying Capacity in Printed Board Design (table of contents) (the newer, measured replacement for the IPC-2221 chart; it shows inner layers are not as hot as the old chart assumes)
• NBS Handbook 100, Copper Wire Tables (1966), p. 4–5 (International Annealed Copper Standard: 0.017241 Ω·mm²/m at 20 °C, temperature coefficient 0.00393 per °C)
• E. B. Rosa, The Self and Mutual Inductances of Linear Conductors, Bulletin of the Bureau of Standards 4(2), 1908 (self-inductance of a straight rectangular bar, L = 2l[ln(2l/(a+b)) + ½ + (a+b)/3l] (cgs, l in cm gives nH))
• E. Hammerstad and Ø. Jensen, Accurate Models for Microstrip Computer-Aided Design, IEEE MTT-S 1980 (closed-form microstrip impedance and effective permittivity, quoted accuracy better than 0.2% for zero-thickness strips)
• JLCPCB PCB manufacturing capabilities (trace/space 0.10/0.10 mm on 1–2 layers and 0.09/0.09 mm multilayer (1 oz); via hole 0.15 mm, via pad 0.25 mm; average hole plating 18 µm; silkscreen line 0.15 mm, text 1.0 mm)

Read on 1 October 2026. Our own choices, not taken from any source: FR-4 εr 4.5, the 0.2 mm prepreg, the 1 nH capacitor mounting inductance, the 10 °C rise, the 0.15 mm default rules and the worked examples. Microstrip widths ignore copper thickness, which makes a real 50 Ω trace slightly narrower. Your fab's stackup and impedance calculator outrank all of this.